1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a fuse circuit, for example, a memory, and to a method of manufacturing the same.
2. Description of Related Art
Hitherto, as semiconductor integrated circuits such as a memory, a semiconductor integrated circuit including a redundant cell has been known. In the semiconductor integrated circuit including a redundant cell, a cell that is rejected as a defective product during a production stage can be replaced by a prepared redundant cell. Thus, a non-defective semiconductor storage device can be shipped. A processing of detecting a defective cell and replacing a redundant cell in a semiconductor integrated circuit is carried out, for example, by cutting out a fuse provided in a redundancy setting circuit in wafer form where plural chips are formed.
FIG. 5 shows a conventional fuse circuit. As shown in FIG. 5, the fuse circuit 100 includes a fuse 101 having one end grounded, a transistor 102 series-connected with the fuse 101, and a detecting circuit 103 connected with a node between the fuse 101 and the transistor 102.
The transistor 102 is turned ON to blow the fuse 101. The fuse detecting circuit 103 injects charges to the node to detect the fuse blowout. That is, when the fuse burns out, charges are accumulated, and the detecting circuit 103 detects High level. When the fuse does not burn out, charges flow to the ground through the fuse 101, and the detecting circuit 103 detects Low level.
Further, a fuse circuit including two fuses has been proposed in place of the fuse circuit including one fuse (for example, Japanese Patent No. 3307349 (Tamaoki), Japanese Unexamined Patent Application Publication No. 2001-118996 (Kin et al.), or the like). For example, a programming circuit as disclosed by Tamaoki offers a non-defective semiconductor storage device by replacing a cell that is rejected as a defective product during a production stage by a prepared redundant cell. The programming circuit is intended to downsize the entire circuit without using a one-shot signal.
FIG. 6 is a circuit diagram showing the programming circuit as disclosed by Tamaoki. As shown in FIG. 6, the programming circuit 200 includes a pair of p-channel MOS (pMOS) transistors 203 and 204 that constitute a flip-flop and a pair of load elements, two fuses 201 and 202. The fuse 202 includes two fuses 202a and 202b that are series-connected. The fuse 201 as one of the two fuses 201 and 202 is used as a programming unit, and the other fuse 202 has a resistance value that is larger than a resistance value of the fuse 101 before the fuse blowout and smaller than a resistance value of the fuse 101 after the fuse blowout.
In the programming circuit 200, the fuse 201 to be blown and the fuse 202 not to be blown are used as a load of the flip-flop, and an amount of current flowing through the fuse 201 is compared with an amount of current flowing through the fuse 202 to determine whether or not the fuse is blown.
That is, if the fuse 201 opens, a resistance value of the fuse 201 is larger than that of the fuse 202. As a result, the pMOS transistor 103 is turned on, and the common node 205 is connected with a power supply voltage VDD. A potential of the common node 205 becomes High, and the pMOS transistor 204 is turned off. The common node 206 is connected with GND, and its potential becomes Low. On the other hand, if the fuse 201 does not open, a resistance value of the fuse 201 is smaller than that of the fuse 202. Thus, the potentials are changed reversely to the above example; the potential of the common node 205 becomes Low, and the potential of the common node 206 becomes High.
As mentioned above, the flip-flop of the programming circuit 200 immediately comes to a stable state irrespective of whether or not the fuse opens, and it is determined whether or not the fuse opens after a signal RESULT is output.
A technique of comparing resistance values of a blown fuse and a reference fuse to generate an accurate fuse optional signal to improve reliability is disclosed by Kin et al. FIG. 7 is a circuit diagram of a fuse optional circuit of an integrated circuit as disclosed by Kin et al.
As shown in FIG. 7, a fuse optional circuit 300 as disclosed by Kin et al. includes a first fuse F1, a second fuse F2, a fuse blowout unit 320, and an optional signal generating unit 350 having an amplifier. The optional signal generating unit 350 includes a first input unit 352, a second input unit 354, and an operational amplifier 356. A MOS transistor NM9 of the first input unit 352 has a gate and drain connected with a first node N11 and a grounded source. A MOS transistor NM10 as the second input unit 354 has a gate and drain connected with a second node N12 and a grounded source. The operational amplifier 356 includes two PMOS transistors PM3 and PM4, and three NMOS transistors NM11 to NM13. A gate of the MOS transistor NM11 is connected with the first node N11, and a gate of the MOS transistor NM12 is connected with the second node N12. A gate of the MOS transistor NM13 receives an enable signal PEFE. Therefore, the operational amplifier 356 amplifies a potential difference between the first node N11 and the second node N12 to output a fuse optional signal POUT of Low level to an inverted output terminal.
However, if one fuse 101 is used as in the conventional fuse circuit, the fuse 101 may be closed due to any factor after blowout, resulting a problem that reliability is insufficient.
Further, in the technique as disclosed by Tamaoki, if a broken fuse is closed due to any factor, although a high-level signal would normally be output from RESULT, a signal of Low level is output in practice, and an erroneous operation may occur. That is, in the technique as disclosed by Tamaoki, two fuses make a pair; the fuse 201 is blown out, and the fuse 202 is used for comparison purpose. A resistance value of the fuse 202 is set (twice) larger than a resistance value of the fuse 201 before blowout and smaller than a resistance value of the blown fuse. However, in the case where the blown fuse 201 closes, if a resistance value of the closed fuse is smaller than a resistance value of the fuse 202 as a reference fuse, it is determined that the fuse 201 does not burn out.
Further, in the fuse optional circuit as disclosed by Kin et al., only the fuse F1 out of the pair of fuses F1 and F2 is blown out, and the fuse F2 cannot burn out. This makes it difficult to ensure that an output voltage level of the terminal POUT in the case where neither the fuse F1 nor the fuse F2 burns out is unequal to an output voltage level of the terminal POUT in the case where the fuse F1 burns out.